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Host Interface (HI08)
Table 6-15. Interface Control Register (ICR) Bit Definitions (Continued)
Bit Number
1
Bit Name
TREQ
Reset Value
0
Transmit Request Enable
Description
Enables host requests via the host request (HREQ or HTRQ) signal when the
transmit data register empty (TXDE) status bit in the ISR is set. If TREQ is
cleared, TXDE interrupts are disabled. If TREQ and TXDE are set, the host
request signal is asserted.
TREQ and RREQ modes (HDRQ = 0)
TREQ
RREQ HREQ Signal
0
0
1
1
0
1
0
1
No interrupts (polling)
RXDF request (interrupt)
TXDE request (interrupt)
RXDF and TXDE request (interrupts)
TREQ and RREQ modes (HDRQ = 1)
TREQ
RREQ HTRQ Signal
HRRQ Signal
0
0
No interrupts (polling)
No interrupts
(polling)
0
1
No interrupts (polling)
RXDF request
(interrupt)
1
1
0
1
TXDE request
(interrupt)
TXDE request
(interrupt)
No interrupts
(polling)
RXDF request
(interrupt)
0
RREQ
0
Receive Request Enable
Controls the HREQ signal for host receive data transfers. RREQ enables host
requests via the host request (HREQ or HRRQ) signal when the receive data
register full (RXDF) status bit in the ISR is set. If RREQ is cleared, RXDF
interrupts are disabled. If RREQ and RXDF are set, the host request signal
(HREQ or HRRQ) is asserted.
6.7.2 Command Vector Register (CVR)
The host processor uses the CVR, an 8-bit read/write register, to cause the DSP56311 to execute
an interrupt. The host command feature is independent of any of the data transfer mechanisms in
the HI08. It causes execution of any of the 128 possible interrupt routines in the DSP core.
Hardware, software, individual, and stop resets clear the CVR bits.
7
HC
6
HV6
5
HV5
4
HV4
3
HV3
2
HV2
1
HV1
0
HV0
Figure 6-16. Command Vector Register (CVR)
DSP56311 User’s Manual, Rev. 2
6-24
Freescale Semiconductor
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